Interrupts

Cortex-A and Cortex-M families have different interrupt and exception models.

Cortex-A has traditional interrupts through IRQ and FIQ. While Cortex-M has vector table supported by NVIC controller.

In Cortex-A, IRQ and FIQ are enabled/disabled using I and F flags in CPSR register.

#Enable IRQ interrupt cpsie i #Enable FIQ interrupt cpsie f

#Disable IRQ interrupt cpsid i #Disable FIQ interrupt cpsid f

One can also directly manipulate I and F flags in CPSR register using msr and mrs instructions.

I_BIT = 0x80 F_BIT = 0x40

#Disables IRQ and FIQ interrupts mrs r0, cpsr orr r0, r0, #I_BIT|F_BIT msr cpsr_c, r0

#Enables IRQ and FIQ interrupts mrs r0, cpsr bic r0, r0, #I_BIT|F_BIT msr cpsr_c, r1

In Cortex-M, there are no IRQ and FIQ. Interrupts can be disabled and enabled using PRIMASK and FAULTMASK registers.

msr PRIMASK, r0 msr FAULTMASK, r0

Even though Cortex-M doesn’t have either CPSR or I and F flags, it has cpsie and cpsid instructions to enable and disable interrupts and fault exceptions. When cpsi instructions are used in Cortex-M micro-controllers, they affect PRIMASK and FAULTMASK rather than CPSR register.

#Enable interrupts and configurable fault handlers (clear PRIMASK) cpsie i #Enable interrupts and fault handlers (clear FAULTMASK) cpsie f

#Disable interrupts and configurable fault handlers (set PRIMASK) cpsid i #Disable interrupts and all fault handlers (set FAULTMASK) cpsid f

Execution modes

Cortex-A processors have several execution modes. Current mode can be read and changed through 5 least significant bits of CPSR register.

C_BIT = 0x1F USER_BITS = 0b10000

mrs r0, cpsr bic r0, #C_BIT orr r0, #USER_BITS msr CPSR_c, r0

Cortex-M processor has only two execution modes. They are Thread and Handler modes. Current mode can be read and changed through least significant bit of control register.

msr CONTROL, r0